The present invention relates to a semiconductor device composed of a plurality of semiconductor chips that are laminated and packaged.
Conventionally, a semiconductor device called a stacked package that is composed of a plurality of semiconductor chips laminated and packaged has been well known. Such stacked packages are roughly classified into the following three types: (1) a package in which semiconductor chips are laminated on a lead frame that is widely used as a common semiconductor package; (2) a package in which semiconductor chips are laminated on a substrate made of a polyimide resin film on which wire patterns are formed; and (3) a package in which semiconductor chips are laminated on a rigid print substrate. The arrangement of the type (2) and a part of the arrangement of the type (3) are characterized in that the package size can be reduced to be approximate to a chip size, and such a package is called as CSP (Chip Size Package).
Combinations of a plurality of semiconductor chips laminated in one stacked package widely vary, including a combination of memory ICs, a combination of memory ICs and logic ICs, a combination of CMOS ICs and bipolar ICs. As a stacked package for use in a portable telephone, packages in which flush memories and SRAMs are laminated are widely used.
FIG. 4 illustrates an example of an arrangement of a CSP-type stacked package. The stacked package 51 is arranged by laminating an IC chip 53 and an IC chip 54 smaller than the IC chip 53, in the stated order, on a CSP substrate 52 as a lamination substrate, comprised of a polyimide substrate or a print substrate. The CSP substrate 52 and the IC chip 53 are made to adhere to each other, as are the IC chip 53 and the IC chip 54, with die bonding adhesive layers 55. The IC chips 53 and 54 are provided with external lead electrodes 53a and 54a, respectively, which are connected with package external lead electrodes 52a provided on the CSP substrate 52.
As a method for connection, as shown in the figure, a technique of wire bonding using wires 56 that are gold lines, for example, is widely applied. The wire bonding technique is also used in the case where the lamination substrate is a lead frame. The package external lead electrodes 52a are connected, via through holes 52b, with the solder ball electrodes 57 provided on a back surface of the CSP substrate 52. Then, on the front surface of the CSP substrate 52, the external lead electrodes 53a and 54a are sealed with resin 58 in a state of being electrically connected with the wires on the CSP substrate 52, whereby a whole of the stacked package 51 is arranged as one package.
Incidentally, in some cases, some of the external lead electrodes of the laminated IC chips are connected, not with the package external lead electrodes, but with external lead electrodes of other laminated IC chips.
However, the foregoing conventional stacked package arrangement raises the following problems in the case where lines are connected by wire bonding.
First of all, a limit on the length L of a wire is about 3 mm, which is determined according to the material characteristic of the wire. Further, a certain wire loop height should be ensured from the bonding surface vertically upward, so as to allow the wire to be bent toward the bonding destination after the start of bonding. Therefore, as a stacked package 61 shown in FIG. 5, the size of the IC chip 62 of the upper stratum is considerably smaller than that of the IC chip 53 of the lower stratum, and hence, in the case where the external lead electrodes 62a of the IC chip 62 and the package external lead electrodes 52a are connected with wires 56 over the IC chip 53 of the lower stratum, the lengths L of the wires 56 occasionally exceed the foregoing limit, depending on the size of the IC chip 53. In this case, there is a possibility that, during bonding, the wires 56 hang down to become in contact with the wires of the IC chip 53, or that the wires 56 are cut by half. In other words, combinations of sizes of IC chips that are allowed to be laminated are considerably limited.
Furthermore, the arrangement of external connection terminals of the package like the solder ball electrodes 57 as shown in FIGS. 4 and 5 is determined depending on a purpose of use, whereas, at which positions in the chip the external lead electrodes of the IC chip should be arranged is determined according to the IC design. Therefore, even in the case where the wires connecting the external lead electrodes of the IC chip and the package external lead electrodes of the lamination substrate are shorter in length than the foregoing limit, the foregoing position relationship of the external connection terminals and the external lead electrodes occasionally causes the wires to cross and become in contact with each other, thereby failing to connect wires.
Conventionally, as an approach to this problem, the following two techniques have been applied. The first technique is as follows: the IC chip lamination substrate is used as a multilaminar wire substrate, and wires are connected from the IC chip to wire-bonding positions on the lamination substrate, so that the bonding positions and the predetermined external connection terminals of the package are connected with wires inside the substrate.
The second technique is a technique disclosed in the Japanese Publication for Laid-Open Patent Application No. 97571/1999 (Tokukaihei 11-97571). According to this technique, a wire arrangement altering substrate that is called an interposer is formed, and wire bonding is carried out from an IC chip to positions of the interposer that are easily subjected to wire bonding. Then, wire bonding is carried out from positions of the interposer that are close to the package external lead electrodes, to the package external lead electrodes. The foregoing bonding positions of two kinds on the interposer are connected with each other via internal wires of the interposer.
However, the foregoing two techniques have the following drawbacks: (1) since the multilaminar wire substrate and the interposer are expensive, this leads to a drastic increase in the package cost; (2) the interposer described in the aforementioned publication requires as high-level a microprocessing technique as that for IC chip fabrication, and a special process and a special site for fabrication of the interposer are required; (3) a thickness of a package increases in the case where the multilaminar wire substrate and the silicon interposer are used, failing to be reduced to a thickness smaller than the predetermined thickness. Furthermore, here, a change of the package thickness produces a need to change the package assembling process, equipments, jigs, instruments, etc., and general-use equipments cannot be shareably used.
Incidentally, in the case where direct connection with wires between the external lead electrodes of the semiconductor chip and the package external lead electrodes requires a wire length excessive of the foregoing limit, the wires may be shortened with use of the foregoing interposer inserted between strata of the semiconductor chips, but there is no change in the situation where inconveniences described in the foregoing (1) through (3) take place.
Thus, conventionally there has been the following problem: that is"", in increasing the number of possible combinations of sizes of semiconductor chips to be laminated, or in preventing wires from becoming in contact with each other in wire bonding for connecting the external lead electrodes of all semiconductor chips laminated with external connection terminals of the package, a drastic rise of the package cost, a considerable increase in the thickness of the package, and a drastic decrease in the package fabrication efficiency are unavoidable. This problem obviously becomes severer as the number of semiconductor chips to be laminated increases.
An object of the present invention is to provide a semiconductor device including a plurality of laminated semiconductor chips as in a stacked package, that is arranged so that the number of possible combinations of sizes of the laminated semiconductor chips can be increased while an increase in the package cost, an increase in the thickness of the package, and deterioration of the package production efficiency can be suppressed.
To achieve the foregoing object, a semiconductor device in accordance with the present invention is a semiconductor device in which a plurality of semiconductor chips equipped with external lead electrodes are laminated on a lamination substrate and packaged in a state in which the external lead electrodes are electrically connected with wires of the lamination substrate, and is characterized by comprising, on a circuit-formed surface of at least one of the semiconductor chips, (i) first electrode pads disposed on a periphery of the chip, (ii) second electrode pads disposed at positions closer to the semiconductor chip immediately above the at least one semiconductor chip, than the positions of the first electrode pads, and (iii) a re-wiring layer having wires (or traces) connecting the first electrode pads and the second electrode pads.
According to the foregoing arrangement, a re-wiring layer as described above is provided on a circuit-formed surface of one semiconductor chip. The re-wiring layer is provided with two kinds of electrode pads, which are first electrode pads provided on a periphery of the chip and second electrode pads provided closer to the semiconductor chip immediately above than the first electrode pads. Further, the first electrode pads and the second electrode pads are connected with traces.
The second electrode pads can be used as, for example, bonding pads for wire bonding with a semiconductor chip of a further upper stratum, as well as use as electrodes for flip-chip bonding with the semiconductor chip immediately above. In the case where the second electrode pads are used as bonding pads, it is possible to extend the electric connection by wire bonding from the first electrode pads via wires. By providing the first and second electrode pads as described above, rather than direct wire bonding from a semiconductor chip of an upper stratum to wires of a lamination substrate, wire bonding should preferably be executed a plurality of times via a semiconductor chip having the re-wiring layer, whereby a length of each wire can be shortened. Therefore, even in the case of a combination of sizes of semiconductor chips that, if wire bonding is only once, would require a length of wires excessive of a limit thereof to connect the semiconductor chips with the lamination substrate, all the wires can be made shorter in length than the limit thereof.
Furthermore, since basically only formation of a wire layer such as a metal thin film and an insulating film on the circuit-formed surface is required, the re-wiring layer has a thickness overwhelmingly smaller than that of an interposer.
Thus, it is possible to provide a semiconductor device including a plurality of laminated semiconductor chips as in a stacked package, that is arranged so that the number of possible combinations of sizes of the laminated semiconductor chips can be increased while an increase in the package cost, an increase in the thickness of the package, and deterioration of the package production efficiency can be suppressed.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.